### E.5 Architecture-Specific Protocol Details

This section describes how the remote protocol is applied to specific target architectures. Also see Standard Target Features, for details of XML target descriptions for each architecture.

#### E.5.1 ARM

##### E.5.1.1 Breakpoint Kinds

These breakpoint kinds are defined for the ‘`Z0`’ and ‘`Z1`’ packets.

2
  16-bit Thumb mode breakpoint.
3
  32-bit Thumb mode (Thumb-2) breakpoint.
4
  32-bit ARM mode breakpoint.

#### E.5.2 MIPS

##### E.5.2.1 Register Packet Format

The following `g`/`G` packets have previously been defined. In the below, some thirty-two bit registers are transferred as sixty-four bits. Those registers should be zero/sign extended (which?) to fill the space allocated. Register bytes are transferred in target byte order. The two nibbles within a register byte are transferred most-significant - least-significant.

MIPS32
  All registers are transferred as thirty-two bit quantities in the order: 32 general-purpose; sr; lo; hi; bad; cause; pc; 32 floating-point registers; fsr; fir; fp.
MIPS64
  All registers are transferred as sixty-four bit quantities (including thirty-two bit registers such as `sr`). The ordering is the same as `MIPS32`.